This invention relates to opto-electric chip integration and, more particularly, to high yield dense integration of opto-electronic devices.
FIGS. 1 and 2 illustrate approaches that have been used in the prior art to attach multiple bottom emitting (or detecting) (also referred to as xe2x80x9cbackside emitting (or detecting)xe2x80x9d) devices to form an integrated electro-optical chip.
According to the approach of FIG. 1, multiple lasers, are formed on a wafer substrate 102 in a conventional manner, as are multiple detectors (interchangeably referred to herein as photodetectors) on their own or on a wafer substrate in common with the lasers. Typically, the portion 104 of the substrate 102 closest to the junction between the optical devices 106, 108 and the substrate 102 is made of a material which is optically transparent at the wavelength at which the optical devices operate. The devices 106, 108 are then processed using conventional techniques such as wet or dry etching to form trenches 112 among the devices 106, 108 which separate them into a series of discrete individual lasers 106 or detector 108 devices. Depending upon the particular technique used, the etched trenches 112 may stop prior to reaching the substrates 102 or extend partly into the substrates 102. Following etching, the substrates 102 and their associated devices are inverted, aligned to the proper location over a Silicon (Si) electronic wafer 114, and bonded to the Si electronic wafer 114 using conventional flip-chip bonding techniques. Following bonding, the entirety of the substrates 102 are thinned extremely thin, by conventional mechanical polishing methods, conventional etch techniques or some combination thereof, to on the order of about 5 microns or less to allow for close optical access to the devices and create an integrated electro-optical wafer 116.
Optionally, the integrated electro-optical wafer 116 is then patterned, using conventional techniques, to protect the individual lasers and the individual detectors are coated with an anti-reflection (AR) coating 118.
A related alternative approach to the technique of FIG. 1 is shown in FIG. 2. In this approach, lasers and detectors are formed as described above. However, when the technique of FIG. 2 used, the trenches 112 are etched into the substrates 102. The substrates 102 and their associated devices are then inverted, aligned to the proper location over a Silicon (Si) electronic wafer 114, and bonded to the Si electronic wafer 114 using conventional flip-chip bonding techniques. Following bonding, the substrates 102 are then wholly removed, by conventional mechanical polishing methods, conventional etch techniques or some combination thereof, to allow for close optical access to the devices and create an integrated electro-optical wafer 116.
Optionally, the integrated electro-optical wafer 116 is then patterned to protect the individual lasers and the individual detectors are coated with an anti-reflection (AR) coating.
The techniques of both FIG. 1 and FIG. 2 make it possible to get optical fibers or optical lenses close enough to the devices to capture the appropriate light without allowing light coming from, or going to, adjacent devices to affect any of those adjacent devices, a problem known as xe2x80x9ccrosstalkxe2x80x9d. Typically, this requires that the separation distance between a device and an optical fiber or optical microlens be less than 100 microns.
Additionally, both techniques ensure that there are no significant absorbing layers over the active region of the devices that will prevent light from escaping since the thinning technique of FIG. 1 reduces the thickness of the entire substrate 102 to about 5 microns or less and the approach of FIG. 2 removes the substrate 102 entirely, leaving multiple wholly independent optical devices.
Both of these techniques however, characteristically create opto-electronic chips that have heat dissipation problems during use and leave the individual devices more sensitive to thermal and mechanical stresses produced during the manufacturing process, thereby reducing individual device lifetimes and, accordingly, decreasing yields and overall chip life.
Moreover, for the approach of both FIG. 1 (where the substrate is extremely thin) and FIG. 2 (where the substrate is completely removed), stresses experienced by the devices are primarily transferred to the very thin optical device layer which is the structurally weakest part of the device.
Thus, there is a need for a way to create an integrated opto-electronic chip that is not as sensitive to the thermal and or structural stresses resulting from processing and/or use.
In addition, a manufacturer of opto-electronic devices has two avenues for obtaining the optical and electronic waferxe2x80x94they can manufacture either or both themselves, or they can obtain one or both from a third party. By manufacturing both the optical devices (interchangeably referred to for simplicity as an xe2x80x9coptical chipxe2x80x9d) and the electronic wafer (interchangeably referred to for simplicity as an xe2x80x9celectronic chipxe2x80x9d), the manufacturer can take measures to ensure that the pads on each are properly placed so as to align with each other when the optical chip is positioned over the electronic chip. However, typically electrical and optical chips are not designed concurrently, even if they are designed and fabricated within the same organization. Thus, even with a single manufacturer, unless there is close coordination within the organization with regard to both the optical and electronic chip design, a lack of correspondence between contact pads on each can easily occurxe2x80x94particularly where one or both are also designed with sales to third parties in mind or integration with devices from other sources is contemplated. Moreover, subsequent improvements or changes in the design of either may necessitate altering the location of the contact pads, thereby introducing a pad misalignment where none previously existed.
Even worse, if the electronic chip is designed to be used with a variety of different optical chips, but the optical chips are commodity stock obtained from third parties (for example, chips containing: topside emitting vertical cavity lasers, bottom emitting vertical cavity lasers, distributed feedback (DFB) or distributed Bragg reflector (DBR) lasers (which each have better chirp and linewidth characteristics for long distance applications), topside receiving detectors or bottom receiving detectors) that are mass manufactured for distribution to multiple unrelated users, it is unlikely that the pads on the optical devices will all be located in the same place, even if they are otherwise compatible with the electronic chip.
For example, as shown in FIG. 3, a single optical device 300 has contact pads 302, 304 placed in the position specified by its manufacturer. A portion of an electronic wafer 306 also has contact pads 308, 310, onto which an optical device can be connected, placed in the position specified by its manufacturer. If the optical device is flipped over, for flip-chip type bonding with the electronic wafer, the contact pads 302, 304, 308, 310, of each will not be aligned as shown in FIG. 4.
This presents a problem in that it limits the ability to xe2x80x9cmix-and matchxe2x80x9d devices. Moreover, if a chip is designed with connection to a particular other chip in mind, and subsequent events create a need to use a different device with a different contact placement, all the planning and coordination done for the original device will be irrelevant to the new device.
Thus, there is a further need for a process that facilitates the ability to mix and match devices without there being any coordination between the designers of either or the use of a standard or common contact placement scheme.
In addition, in some cases it is sometimes desirable to coat some of the devices, specifically the detectors, with an AR coating.
An AR coating prevents light from hitting the top of a detector device and being reflected at the detector-air interface due to the differences in the indexes of refraction. This is important for detectors because reflected light is light that does not enter the detector itself and hence can not be converted into electrical signals (i.e. it is xe2x80x98lost lightxe2x80x99 from a system point of view). Thus an AR coating optimizes the collection efficiency of the detector because it prevents light from being reflected at that interface.
Lasers however, require a top mirror of very high in reflectivity in order to operate. AR coating on a laser changes the reflectivity of the top mirror. As a result, at a minimum it will detrimentally affect the lasing action of the laser, if not prevent it from lasing altogether.
If a wafer has both lasers and detectors in an array, in order to AR coat only the detectors, conventional wisdom would mandate that special patterning of the wafer be performed to protect the lasers during the AR coating deposition phase to ensure that those laser devices were not covered by the AR coating.
The protection or disparate treatment of the various different devices on the wafer requires extra processing steps, which costs time, and hence increases the cost of processing. It also introduces the possibility of damaging the protected devices. Finally, it forces the electrical contact pads to be protected as well.
In addition disparate treatment of devices causes other processing problems when the processing must be performed on a chip having electrical contact pads in the same area. For example, if a chip has electrical contacts near the devices and electroplating, electroless plating, thermal evaporates, e-beam evaporated or sputtering techniques are used to place solder on the contact pads, the height of the resulting solder bumps, renders it difficult to pattern areas to protect lasers from AR coating because the solder bumps are much taller than the optical devices.
Prior art lacks a way to eliminate the need to pattern a protective layer over the lasers while allowing the entire wafer (i.e. lasers and detectors) to be AR coated.
Thus, there is a further need for a way to permit integration of multiple types of devices on an electronic chip so that any additional processing steps, such as anti-reflection coating, can be done on the whole wafer at one time and without special patterning after integration.
We have devised a way of creating electro-optical chips that, in various implementation variants, overcome one or more of the above shortcomings of the prior art, resulting in higher yields and longer life (i.e. more reliable) devices. In particular, we have devised a way to create opto-electronic chips which, in some variants, provides one or more of the following advantages: allows use of a lower operating current, thereby reducing power consumption and heat generation; provides better dissipation of heat that is generated, allowing the lasers to run at lower temperatures thereby increasing their usable life and/or providing better wavelength control; and/or having a higher structural integrity resulting in fewer defects and increased device lifetime.
We have further devised a way to integrate optical and electronic chips to create an integrated opto-electronic device, irrespective of whether the component devices are manufactured in a coordinated manner or have compatibly matching electrical contact points.
Still further, we have devised a way to create an integrated opto-electronic device that allows for an entire wafer having disparate devices to be AR coated, without special processing to protect the lasers or affecting their ability to lase.
When integrating optical devices intimately with electronic chips, four attributes are desirable to create reliable integrated optical devices.
First, it must be possible to get optical fibers or optical lenses close enough to capture the light without crosstalk. Second, there must be no absorbing layers above the active region of the devices that would prevent light from escaping or entering the particular devices. Third, there should be a large enough thermal mass attached to the devices to allow for efficient heat dissipation. Fourth, the structural integrity of the devices should be maintained during processing so that stresses or strains experienced by the devices do not impact device performance.
As noted above, the approaches of FIG. 1 and FIG. 2 can satisfy the first two attributes however, neither of those approaches satisfies the third or fourth since neither approach results in a large thermal mass attached to the devices (i.e. the substrate of the devices) or reduces stresses on the devices.
Although applicants are unaware of any such case existing in the prior art or otherwise, the approach of FIG. 1 could potentially be made to satisfy the fourth attribute by leaving a thicker layer of substrate on the device. However, this could likely only be accomplished if the operating wavelength of the particular devices were very transparent to the wavelength at which the devices operated. Moreover, for many cases, this would reduce, if not destroy, the ability to satisfy the first attribute and would likely also detrimentally impact the operation of a laser device unless the laser were redesigned to emit into, for example, a semiconductor material rather than being designed to emit into air. In addition, if thicker substrates were left, it would be necessary to AR coat the structure to prevent optical feedback into the laser. In addition, such an approach would likely also foreclose the use of commercially purchasable prefabricated semiconductor optical devices, such as most third party offered Vertical Cavity Surface Emitting Lasers (VCSELs), Distributed Feed Back (DFB) lasers or Distributed Bragg Reflector (DBR) lasers.
In sum, we have devised a way to closely integrate optical devices and an electronic chip to create an opto-electronic chip that can satisfy all four attributes. Moreover we can do so using devices acquired from third parties when desired. Still further, we offer advantages over the prior art in terms of lower cost to produce, higher yield and improved operating life.
A first aspect of the invention involves a method of creating a hybridized chip using a top active optical device, having a substrate including a first side and active device contacts on the first side, the top active optical device also being on the first side, combined with an electronic chip having electronic chip contacts, when at least some of the active device contacts are not aligned with at least some of the electronic chip contacts, each of the at least some active device contacts having an electrically corresponding electronic chip contact. The method involves creating sidewalls defining openings in the substrate, extending from the first side at the active device contacts to a bottom of the substrate opposite the first side, at points substantially coincident with the active device contacts; making the sidewalls electrically conductive; and connecting the points and the electronic chip contacts with an electrically conductive material.
A second aspect of the invention involves a hybridized chip has at least one top active optical device coupled to an electronic chip, the hybridized chip having been created using a described method.
A third aspect of the invention involves a method of connecting two chips, one of which being a topside active chip, each of the two chips having electrically corresponding contacts to be joined together that are physically mismatched relative to each other. The method involves creating electrically conductive paths on an insulator, each of the electrically conductive paths extending between physical locations of contacts of one of the two chips and physical locations of the electrically corresponding contacts on the other of the two chips.
These and other aspects described herein, or resulting from the using teachings contained herein, provide advantages and benefits over the prior art.
The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.